/////////////////////////////////////////////////////////////////////////////
// Name of module : mcu_top                                                //
// Func           : top level                                              //
// Author         : heguang                                                //
// version 1.0    : made in Date: 2019.06.21                               //
/////////////////////////////////////////////////////////////////////////////

`timescale 1ns/10ps
module mcu_top #(
parameter [23:0] FLASH_BIAS       =  24'hB1CE6
)
(   
                        input  wire             sclk                 ,
                        //clock and reset
                        output reg              clk_mcu              ,
                        input  wire             resetb               ,

                        //uart
                        input  wire             UART_RXD             ,
                        input  wire             UART_CTS_n           ,
                        output wire             UART_TXD             ,
                        output wire             UART_RTS_n           ,

                        //jtag
                        input  wire             JTRST_n              ,
                        input  wire             JTCK                 ,
                        input  wire             JTDI                 ,
                        input  wire             JTMS                 ,
                        output wire             JTDO                 ,

                        //ram access
                        input  wire             EXT_RAM_EN           ,
                        input  wire             EXT_RAM_WR           ,
                        input  wire [13:0]      EXT_RAM_ADDR         ,    //in word
                        input  wire [3:0]       EXT_RAM_BYTE_EN      ,
                        input  wire [31:0]      EXT_RAM_WDATA        ,
                        output wire [31:0]      EXT_RAM_RDATA        ,


                         //flash
                        output wire             FLASH_SCK            ,
                        output wire             FLASH_CS_N           ,

                        inout  tri              FLASH_SI             ,
                        inout  tri              FLASH_SO             ,

                        //gpio
                        input  wire [7:0]  GPIO0_I              ,
                        output wire [7:0]  GPIO0_O              ,
                        output wire [7:0]  nGPEN0               ,


                        input  wire [7:0]  GPIO1_I              ,
                        output wire [7:0]  GPIO1_O              ,
                        output wire [7:0]  nGPEN1               ,

                        input  wire [7:0]  GPIO2_I              ,
                        output wire [7:0]  GPIO2_O              ,
                        output wire [7:0]  nGPEN2               ,
                        
                        output wire             O_INI_IP             ,

                        output wire [3:0]       apb_sel              ,
                        output wire [31:0]      apb_addr             ,
                        output wire             apb_rw_en            ,
                        output wire [31:0]      apb_wdata            ,
                        input  wire [31:0]      apb_rdata0           ,
                        input  wire [31:0]      apb_rdata1           ,
                        input  wire [31:0]      apb_rdata2           ,
                        input  wire [31:0]      apb_rdata3           
                        );


wire [31:0]   hwdata              ;
wire [31:0]   haddr               ;
wire          hwrite              ;// 1 - Write, 0 - Read
wire [2:0]    hsize               ;
wire          hsel                ;
wire [1:0]    htrans              ;
wire [31:0]   hrdata              ;
wire          hready_out          ;

wire                FLASH_IO0_SI    ;
wire                FLASH_IO0_SI_i  ;
wire                FLASH_SI_OE     ;

wire                FLASH_IO1_SO    ;
wire                FLASH_IO1_SO_i  ;
wire                FLASH_SO_OE     ;

wire        clk_mcu_div;
assign clk_mcu_div = ~sclk;
always@(posedge clk_mcu_div)begin
    clk_mcu <= ~clk_mcu;
end

assign FLASH_IO0_SI_i = FLASH_SI;
assign FLASH_SI = FLASH_SI_OE ?   FLASH_IO0_SI : 1'bz   ;

assign FLASH_IO1_SO_i = FLASH_SO;
assign FLASH_SO = FLASH_SO_OE ?  FLASH_IO1_SO : 1'bZ ;

alta_mcu_top    alta_mcu_topEx01
(
    .CLK                    (    clk_mcu                    ),
    .POR_n                  (    resetb                     ),               //(     resetb_mcu      ),
    .EXT_CPU_RST_n          (    1'b1                       ),

    .UART_RXD               (    UART_RXD                   ),
    .UART_CTS_n             (    UART_CTS_n                 ),
    .UART_TXD               (    UART_TXD                   ),
    .UART_RTS_n             (    UART_RTS_n                 ),

    .JTRST_n                (    JTRST_n                    ),
    .JTCK                   (    JTCK                       ),
    .JTDI                   (    JTDI                       ),
    .JTMS                   (    JTMS                       ),
    .JTDO                   (    JTDO                       ),

    .EXT_RAM_EN             (    EXT_RAM_EN                 ),
    .EXT_RAM_WR             (    EXT_RAM_WR                 ),
    .EXT_RAM_ADDR           (    EXT_RAM_ADDR               ),
    .EXT_RAM_BYTE_EN        (    EXT_RAM_BYTE_EN            ),
    .EXT_RAM_WDATA          (    EXT_RAM_WDATA              ),
    .EXT_RAM_RDATA          (    EXT_RAM_RDATA              ),

    .HRESP_EXT              (    hresp                      ),
    .HREADY_OUT_EXT         (    hready_out                 ),
    .HRDATA_EXT             (    hrdata                     ),
    .HTRANS_EXT             (    htrans                     ),
    .HADDR_EXT              (    haddr                      ),
    .HWRITE_EXT             (    hwrite                     ),
    .HSEL_EXT               (    hsel                       ),
    .HWDATA_EXT             (    hwdata                     ),
    .HSIZE_EXT              (    hsize                      ),
    .HREADY_IN_EXT          (                               ),

    .FLASH_SCK              (   FLASH_SCK                   ),
    .FLASH_CS_n             (   FLASH_CS_N                  ),

    .FLASH_BIAS             (   FLASH_BIAS                  ),

    .FLASH_IO0_SI           (   FLASH_IO0_SI                ),
    .FLASH_IO0_SI_i         (   FLASH_IO0_SI_i              ),
    .FLASH_SI_OE            (   FLASH_SI_OE                 ),

    .FLASH_IO1_SO           (   FLASH_IO1_SO                ),
    .FLASH_IO1_SO_i         (   FLASH_IO1_SO_i              ),
    .FLASH_SO_OE            (   FLASH_SO_OE                 ),

    .FLASH_IO2_WPn          (                               ),
    .FLASH_IO2_WPn_i        (       1'b1                    ),
    .WPn_IO2_OE             (                               ),

    .FLASH_IO3_HOLDn        (                               ),
    .FLASH_IO3_HOLDn_i      (       1'b1                    ),
    .HOLDn_IO3_OE           (                               ),

    .GPIO0_I                ( GPIO0_I          ),
    .GPIO0_O                ( GPIO0_O          ),
    .nGPEN0                 ( nGPEN0           ),
    .GPIO1_I                ( GPIO1_I          ),
    .GPIO1_O                ( GPIO1_O          ),
    .nGPEN1                 ( nGPEN1           ),
    .GPIO2_I                ( GPIO2_I          ),
    .GPIO2_O                ( GPIO2_O          ),
    .nGPEN2                 ( nGPEN2           ),
    .O_INI_IP               ( O_INI_IP         )
) ;

ahb2ram_4 ahb2ram_3_inst(
                .hclk       ( clk_mcu               ),
                .hresetn    ( resetb                ),
                
                .hwdata     ( hwdata                ),
                .haddr      ( haddr                 ),
                .hwrite     ( hwrite                ),// 1 - Write, 0 - Read
                .hsize      ( hsize                 ),
                .hsel       ( hsel                  ),
                .htrans     ( htrans                ),
                .hrdata     ( hrdata                ),
                .hready_out ( hready_out            ),

                .sclk       ( sclk                  ),
                
                .sel        ( apb_sel               ),
                .addr       ( apb_addr              ),
                .wr_en      ( apb_rw_en             ),
                .wdata      ( apb_wdata             ),
                .rdata0     ( apb_rdata0            ),
                .rdata1     ( apb_rdata1            ),
                .rdata2     ( apb_rdata2            ),
                .rdata3     ( apb_rdata3            )
                );

assign hresp = 2'b0;
endmodule